(1) Field of the Invention
The present invention relates to a semiconductor circuit, more particularly, to a circuit applied in, for example, a static semiconductor memory for generating a clock signal when an input signal, such as the address signal, changes.
(2) Description of the Related Art
A static memory generally does not need a clock signal, in contrast to a dynamic memory, which always needs a clock signal. Some special static memories, however, use clock signals to represent address changes, write instructions, or power downs, to decrease the access time, and so forth. Prior art static memories employing clock signals are disclosed in, for example:
Japanese Unexamined Patent Publication (Kokai) No. 57-69586, published on Apr. 28, 1982, filed on Oct. 15, 1980, inventor: Atsushi Oritani, applicant: Fujitsu Limited;
Japanese Unexamined Patent Publication No. 58-3186, published on Jan. 8, 1983, filed on June 30, 1981, inventor: Atsushi Oritani, applicant: Fujitsu Limited;
Japanese Unexamined Patent Publication No. 58-41485, published on Mar. 10, 1983, filed on Sept. 1, 1981, inventor: Keizo Aoyama, applicant: Fujitsu Limited;
Japanese Unexamined Patent Publication No. 58-41486, published on Mar. 10, 1983, filed on Sept. 1, 1981, inventor: Keizo Aoyama, applicant: Fujitsu Limited;
Japanese Unexamined Patent Publication No. 59-3783, published on Jan. 10, 1984, filed on June 30, 1982, inventor: Atsushi Oritani, applicant: Fujitsu Limited;
Japanese Unexamined Patent Publication No. 59-63091, published on Apr. 10, 1984, filed on Sept. 30, 1982, inventor: Eiji Noguchi, applicant: Fujitsu Limited; and
Japanese Unexamined Patent Publication No. 59-63094, published on Apr. 10, 1984, filed on Oct. 4, 1982, inventor: Keizo Aoyama et al, applicant: Fujitsu Limited.
In the static memories using the clock signals, when a memory cell of the static memory is accessed, a bit-line pair is temporarily short-circuited to be the same potential by applying a clock signal and then is changed to a high level (H) or a low (L) level in accordance with the data stored in the memory cell. This decreases the access time in comparison with a circuit not using a clock signal, wherein the change is effected from an H or L state, depending on the stored data previously read, to an H or L state, depending on the stored data which is to be currently read. This short-circuiting is also effected in a sense amplifier, wherein the response speed for currently read data is increased by resetting the output signals by the clock signal before starting the operation of the sense amplifier.
A clock signal representing a change of an input signal, such as an address signal, is conventionally generated by taking a logical OR of pulses generated by changes of respective input signals. For example, the address signals used for the input signals are 10 bits in a 1K-memory, 11 bits in a 2K-memory, and so forth. From each bit of the address signals, a complementary pair of bit A.sub.i and its inverted bit A.sub.i (i=0, 1, 2, . . . ) is obtained, which are input to a decoder to act as a signal for selecting a word line or a bit line. A pulse generating circuit for each of the above-mentioned pulses is provided in an address inverter. The pulse generated from the pulse generating circuit is supplied to the OR gate for obtaining the above-mentioned logical OR.
However, the clock signal thus generated has a problem in that, when the rising time and the falling time of the input siganls are indefinite, the width of the clock signal changes depending on the input signals. When the input signals are input address signals, this problem is caused because (1) since the address inverters and, accordingly, the above-mentioned pulse generating circuits are spread over a certain area of a memory chip, the wiring lengths between each pulse generating circuit and the OR gate are different from each other, so that the timings of the output pulses reaching the OR gate are slightly different; (2) since the pulses output from the respective pulse generating circuits do not always have the same pulse widths, the pulse widths of the clock signals and the falling timing of the clock pulses are changed depending on which address signal is changed; (3) there is a case when a plurality of address signals (bits) are changed almost simultaneously but with slightly different timings, and, in this case, since the clock width is a logical sum of the plurality of pulses, the pulse width has a tendency to expand because the pulse widths generated by the respective changes of the address signals are not always the same.
It is not preferable, in order to ensure the short- circuiting of the pair of bit lines and so forth, that the clock pulse width vary depending on which of the input signals or which of the input address signals changes. Therefore, for the above-mentioned reset of the bit line pair or of the sense amplifier, the clock signal is preferred to have a constant pulse width and constant falling and rising timings in response to each change of the input signals.